1. Field of the Invention
The present invention relates generally to programmable logic devices, and more particularly to an improved programmable array logic-based erasable-programmable logic device (EPLD) including a flexible-function carry chain architecture.
2. Description of the Related Art
Basic PLDs (programmable logic devices) are based on a programmable logic array, normally composed of a specific number of input lines connected through a programmable array to the input terminals of a set of AND logic gates, the output terminals of which are in turn connected to the input terminals of a fixed or programmable array of OR gates. Devices are called PAL.RTM.-based when the programmable array logic includes a fixed OR array.
New kinds of erasable PAL-based devices (chips) have appeared in recent years, such as the XC7300.TM. EPLD family of devices, provided by Xilinx, Inc. having an address at 2100 Logic Drive, San Jose, Calif., that features on each chip a plurality of structurally and functionally identical function blocks and has a programmable interconnect resource which interconnects the function blocks. The interconnect resource in the XILINX device is designated the Universal Interconnect Matrix (UIM). Each function block on the chip includes a programmable AND array and several macrocells so that the block functions as a stand alone PAL. With an appropriate configuration, a block can be used in a manner logically separate from the rest of the chip or can be functionally integrated with the rest of the chip.
FIG. 1 illustrates in simplified form the architecture of the XILINX XC7236.TM. chip, a PAL-based EPLD. Four configurable function blocks FB1, FB2, FB3, FB4 are interconnected by a central UIM. Each of the four blocks FB1-FB4 receives input lines from the UIM, and connects by output lines to chip input/output pads I/O and/or back into the UIM. Blocks FB2, FB3, FB4 receive input lines coming from the I/O pads as well. Each block FB1-FB4 has carry-in and carry-out lines as well as shift-in and shift-out lines, with the "in" lines of each block being connected to the "out" lines of a previous block and the "out" lines of each block being connected to the "in" lines of a next block, forming loops as illustrated between the blocks. Each of the function blocks FB1-FB4 includes nine macrocells and a programmable AND array (an example of which is shown in FIG. 2) which is driven by the input lines from the UIM and input lines coming directly from the I/O pads. The XC7236 device thus contains 36 macrocells having identical structures.
FIG. 2 shows the schematic diagram of one of the macrocells FB1, and the AND array present in each function block of the XC7236 chip. Macrocells MC1-MC9 in the block (FIG. 2 shows MC1 only) are driven by the product terms (P-terms) derived from the programmable AND array AA2 in the same block. Five P-terms PP1-PP5, PP6-PP10 . . . PP41-PP45 are private to each of the nine macrocells in the block, while an additional twelve P-terms SP1-SP12 are shared among the nine macrocells in the block. Four of the private P-terms PP1-PP4 can be selectively (through programming of programmable switch elements SW1-SW4) logically ORed by gate OR1 together with up to four shared P-terms SP9-SP12 and drive the D1 data input terminal of an arithmetic logic unit ALU. The other data input terminal D2 of the ALU is driven by the output signal of gate OR2 which logically ORs the fifth private P-term PP5 and up to eight of the remaining shared P-terms SP1-SP8. The four private P-terms PP1-PP4 can be programmed for other purposes; for instance the private P-term PP1 can be used as a dedicated clock signal for the flip-flop FF; P-term PP2 can be the Output Enable signal OE; and the P-terms PP3 and PP4 can be the asynchronous SET S and RESET R signals, respectively, for the flip-flop FF.
The ALU can be placed into two modes, logic mode and arithmetic mode. In logic mode, the ALU is a 2-input function generator that can be programmed to generate any Boolean function of the output signals of logic gates OR1 and OR2 provided on data input terminals D1 and D2, respectively. In arithmetic mode, the ALU can be programmed to generate the arithmetic sum of two operands, combined with a carry signal coming from the next lower order macrocell. The arithmetically driven ALU also feeds a carry output signal C.sub.out to the ALU of the next higher order macrocell.
A logic block with macrocells of the kind shown in FIG. 2 is both complex and highly configurable and can implement a variety of logic functions by programming the configuration bits such as CB1-CB7, switches such as SW1-SW16, tri-state buffers such as TSB1 and TSB2, and multiplexers in the ALU. However, such high configurability requires a large number of logic gates in the speed path, thereby causing more propagation delay than might be desired. Also, delay caused by routing signals through the UIM between function blocks limits the speed of programmable devices. Thus, high speed and high flexibility/configurability of logic functions are generally in conflict with each other and must be traded off in such prior art devices.
Utilization Of The ALU
One possible path, therefore, for increasing device configurability without sacrificing speed is to improve the configurability of existing circuit elements. Many integrated circuit designs need to implement arithmetic as well as logic functions. In available non-programmable VLSI integrated circuit devices, such as Application Specific Integrated Circuits (ASICs), a series of single bit ALU's can be used to provide multi-bit wide ALU functionality. In these devices, a hard-wired carry function is used to provide an arithmetic carry when the ALU is being used in its arithmetic mode. The appropriate carry function for the specific design can thereby be provided, and wide non-arithmetic logic functions are simply built as necessary since there is little need for a flexible carry that can be used to carry logic functions as well as arithmetic functions.
In programmable devices, dual function carry is implemented, for example, via the dual function ALU illustrated in FIG. 3. The ALU of FIG. 3 is incorporated into the function block as shown in FIG. 2. FIG. 4 illustrates two ALUs implemented as programmable adder circuits. Note that carry blocks 10 include the carry circuitry shown in FIG. 3. Adder blocks 15 typically comprise programmable 2-bit function generators configured as XOR gates for completing the adder circuit, as shown, but are capable of reprogramming to any other basic 2-bit logic function.
Such an adder circuit can be designed into and implemented by the macrocells efficiently. Moreover, because adder logic is modular, each macrocell in a device can contain an identical programmable adder circuit. By passing carry information across adjacent macrocells, a fast and efficient adder chain may be implemented. Such blocks are useful for adders and comparator circuits, but have limited utility as functional logic due to their lack of full programmability.
Accordingly, there is a need in the industry for additional logic capability within macrocells to enable common functions other than adders to be implemented efficiently. In particular, because additional routing lines within a chip can increase chip size, it is desirable to have a programmable function that can implement adders and other functions while using only one set of lines to pass information between macrocells.